Acceleration of an FPGA router

In this article we describe our experience and progress in accelerating an FPGA router. Placement and routing is undoubtly the most time-consuming process in automatic chip design or connguring pro-grammable logic devices as reconngurable computing elements. Our goal is to accelerate routing of FPGAs by 10 fold with a combination of workstation clusters and hardware acceleration. Coarse-grain parallelism is exploited by having several processors route separate groups of nets in parallel. A hardware accelerator is presented which exploits the ne-grain parallelism in routing individual nets.